A circuit for storing low addressability halftone arrays for a high addressability printer in a reduced amount of memory by storing high addressability arrays at one location per sub pixel, and low addressability pixels at one location per pixel, and by arranging the halftone generator to output each low addressability pixel a number of times to match the number of sub pixels per pixel.
In a regular printer, halftone arrays are stored at one location per pixel. As each pixel is received, it is compared to the array output and then output as either a ONE or a ZERO, depending on the comparison. Then the next array value is compared to the next pixel, etc.
In a high addressability printer, each pixel is divided up into a number of sub pixels, and there is an array location for each. For a numerical example, assume an addressability factor of 4. Then each pixel will be divided up into 4 sub pixels, and four comparisons will be used to generate 4 sub pixels to be printed. The result is that the regular 4 by 4 array must now be 16 by 4, and more memory is needed.
A problem arises when large numbers of large dots, such as 128 by 128 pixels, are needed, in which case the amount of memory for the storage of all the arrays becomes excessive. A method of reducing the storage requirement is needed.